//============================================
// Define VDD and VSS
//============================================
VVDD (VDD 0) vsource dc=pvdd  // VDD source
VVSS (VSS 0) vsource dc=0 // Ground
VVWRT (write 0) vsource type=pulse val0=0 val1=0 delay=0n rise=.01n fall=.01n width=.45n period=4n
VVIN (IN 0) vsource type=pulse val0=0 val1=pvdd rise=.01n fall=.01n width=12n period=12n
VVRD (read 0) vsource type=pulse val0=0 val1=0 rise=.01n delay=2n fall=.01n width=.55n period=6n
VVDT (data 0) vsource type=pulse val0=pvdd val1=0 rise=.01n delay=0n fall=.01n width=3n period=6n

//3input NAND
 subckt NAND3 A0 A1 A2 out VDD VSS
 parameters wn = 450n wp = 225n lpn = 50n
  M0 (out A0 VDD VDD)PMOS_VTL w =wp l = lpn
  M1 (out A1 VDD VDD)PMOS_VTL w =wp l = lpn
  M2 (out A2 VDD VDD)PMOS_VTL w =wp l = lpn
  M4 (out A0 p1 VSS)NMOS_VTL w =wn l = lpn
  M5 (p1 A1 p2 VSS)NMOS_VTL w =wn l = lpn
  M6 (p2 A2 VSS VSS)NMOS_VTL w =wn l = lpn
 ends NAND3

 //2input NAND
 subckt NAND2 A3 A4 out VDD VSS
 parameters wn = 450n wp = 225n lpn = 50n
  M0 (out A3 VDD VDD)PMOS_VTL w =wp l = lpn
  M1 (out A4 VDD VDD)PMOS_VTL w =wp l = lpn
  M4 (out A3 p1 VSS)NMOS_VTL w =wn l = lpn
  M5 (p1 A4 VSS VSS)NMOS_VTL w =wn l = lpn
 ends NAND2


 //2input NOR
 subckt NOR2 B0 B1 out VDD VSS
  parameters wn = 102n wp = 407n lpn = 50n
  M0 (out B0 VSS VSS)NMOS_VTL w =wn l = lpn
  M1 (out B1 VSS VSS)NMOS_VTL w =wn l = lpn
  M2 (out B0 p4 VDD)PMOS_VTL w =wp l = lpn
  M3 (p4 B1 VDD VDD)PMOS_VTL w =wp l = lpn
 ends NOR2

 //3input NOR
 subckt NOR3 B0 B1 B2 out VDD VSS
  parameters wn = 102n wp = 407n lpn = 50n
  M0 (out B0 VSS VSS)NMOS_VTL w =wn l = lpn
  M1 (out B1 VSS VSS)NMOS_VTL w =wn l = lpn
  M2 (out B2 VSS VSS)NMOS_VTL w =wn l = lpn
  M3 (out B0 p4 VDD)PMOS_VTL w =wp l = lpn
  M4 (p4 B1 p5 VDD)PMOS_VTL w =wp l = lpn
  M5 (p5 B2 VDD VDD)PMOS_VTL w =wp l = lpn
 ends NOR3

// 4input NAND
subckt NAND4 A0 A1 A2 A3 out VDD VSS
parameters wn = 450n wp = 225n lpn = 50n
 M0 (out A0 VDD VDD) PMOS_VTL w =wp l = lpn
 M1 (out A1 VDD VDD) PMOS_VTL w =wp l = lpn
 M2 (out A2 VDD VDD) PMOS_VTL w =wp l = lpn
 M3 (out A3 VDD VDD) PMOS_VTL w =wp l = lpn
 M4 (out A0 p1 VSS) NMOS_VTL w =wn l = lpn
 M5 (p1 A1 p2 VSS) NMOS_VTL w =wn l = lpn
 M6 (p2 A2 p3 VSS) NMOS_VTL w =wn l = lpn
 M7 (p3 A3 VSS VSS) NMOS_VTL w =wn l = lpn
ends NAND4

 //standard inverter
 subckt Inverter VDD VSS in out
 parameters wp=180n wn=90n lpn=50n
         M0 (out in VDD VDD) PMOS_VTL w =wp l = lpn
         M1 (out in VSS VSS) NMOS_VTL w =wn l = lpn
 ends Inverter


 //Predecoder (3 - 8, 2 - 4)
 subckt wordDecoder VDD VSS in0 in1 in2 in3 in4 inb0 inb1 inb2 inb3 inb4 out00000 out00001 out00010 out00011 out00100 out00101 out00110 out00111 out01000 out01001 out01010 out01011 out01100 out01101 out01110 out01111 out10000 out10001 out10010 out10011 out10100 out10101 out10110 out10111 out11000 out11001 out11010 out11011 out11100 out11101 out11110 out11111

 // Decode addr[0:2]
 Nc1 (inb0 inb1 inb2 out000 VDD VSS) NAND3
 Nc2 (inb0 inb1 in2 out001 VDD VSS) NAND3
 Nc3 (inb0 in1 inb2  out010 VDD VSS) NAND3
 Nc4 (inb0 in1 in2  out011 VDD VSS) NAND3
 Nc5 (in0 inb1 inb2  out100 VDD VSS) NAND3
 Nc6 (in0 inb1 in2  out101 VDD VSS) NAND3
 Nc7 (in0 in1 inb2   out110 VDD VSS) NAND3
 Nc8 (in0 in1 in2   out111 VDD VSS) NAND3

 // Decode addr[3:4]
Nc9 (inb3 inb4 out00 VDD VSS) NAND2
 Nc10 (inb3 in4 out01 VDD VSS) NAND2
 Nc11 (in3 inb4 out10 VDD VSS) NAND2
 Nc12 (in3 in4 out11 VDD VSS) NAND2

 // word decode
 Oc1 (out00 out000 out00000 VDD VSS) NOR2
 Oc2 (out00 out001 out00001 VDD VSS) NOR2
 Oc3 (out00 out010 out00010 VDD VSS) NOR2
 Oc4 (out00 out011 out00011 VDD VSS) NOR2
 Oc5 (out00 out100 out00100 VDD VSS) NOR2
 Oc6 (out00 out101 out00101 VDD VSS) NOR2
 Oc7 (out00 out110 out00110 VDD VSS) NOR2
 Oc8 (out00 out111 out00111 VDD VSS) NOR2
 Oc9 (out01 out000 out01000 VDD VSS) NOR2
 Oc10 (out01 out001 out01001 VDD VSS) NOR2
 Oc11 (out01 out010 out01010 VDD VSS) NOR2
 Oc12 (out01 out011 out01011 VDD VSS) NOR2
 Oc13 (out01 out100 out01100 VDD VSS) NOR2
 Oc14 (out01 out101 out01101 VDD VSS) NOR2
 Oc15 (out01 out110 out01110 VDD VSS) NOR2
 Oc16 (out01 out111 out01111 VDD VSS) NOR2
 Oc17 (out10 out000 out10000 VDD VSS) NOR2
 Oc18 (out10 out001 out10001 VDD VSS) NOR2
 Oc19 (out10 out010 out10010 VDD VSS) NOR2
 Oc20 (out10 out011 out10011 VDD VSS) NOR2
 Oc21 (out10 out100 out10100 VDD VSS) NOR2
 Oc22 (out10 out101 out10101 VDD VSS) NOR2
 Oc23 (out10 out110 out10110 VDD VSS) NOR2
 Oc24 (out10 out111 out10111 VDD VSS) NOR2
 Oc25 (out11 out000 out11000 VDD VSS) NOR2
 Oc26 (out11 out001 out11001 VDD VSS) NOR2
 Oc27 (out11 out010 out11010 VDD VSS) NOR2
 Oc28 (out11 out011 out11011 VDD VSS) NOR2
 Oc29 (out11 out100 out11100 VDD VSS) NOR2
 Oc30 (out11 out101 out11101 VDD VSS) NOR2
 Oc31 (out11 out110 out11110 VDD VSS) NOR2
 Oc32 (out11 out111 out11111 VDD VSS) NOR2
 ends wordDecoder

subckt enabledInverter VDD VSS in en enb out
parameters wp=360n wn=180n lpn=50n
 M0 (net0 in VDD VDD) PMOS_VTL w=wp l=lpn
 M1 (out enb net0 VDD) PMOS_VTL w=wp l=lpn
 M2 (out en net1 VSS) NMOS_VTL w=wn l=lpn
 M3 (net1 in VSS VSS) NMOS_VTL w=wn l=lpn
ends enabledInverter

subckt TGate VDD VSS in en enb out
parameters wp=180n wn=90n lpn=50n
 M0 (out enb in VDD) PMOS_VTL w=wp l=lpn
 M1 (out en in VSS) NMOS_VTL w=wn l=lpn
ends TGate

//BL
subckt BL ADDRen WR RD Data BL BLB VDD VSS
 // Calculate opposites
 I0 (VDD VSS ADDRen ADDRb) Inverter
 I1 (VDD VSS RD RDB) Inverter
 I2 (VDD VSS WR WRB) Inverter

 // Calculate precharge
 N0 (WRB RDB net0 VDD VSS) NAND2
 I3 (VDD VSS net0 net1) Inverter
 N1 (net1 ADDRb preb VDD VSS) NOR2

 // precharge logic
 M0 (net2 preb VDD VDD) PMOS_VTL w=180n l=50n
 M1 (net3 preb VDD VDD) PMOS_VTL w=180n l=50n
 I4 (VDD VSS Data Datab) Inverter
 N2 (ADDRen WR drenb VDD VSS) NAND2
 I5 (VDD VSS drenb dren) Inverter
 T0 (VDD VSS Datab dren drenb net3) TGate
 T1 (VDD VSS Data dren drenb net2) TGate
 N3 (ADDRen WRB RD enable VDD VSS) NAND3
 I6 (VDD VSS enable enableb) Inverter
 I7 (VDD VSS net2 net4) Inverter wp=360n wn=180n
 I8 (VDD VSS net4 enable enableb BL) enabledInverter
 I9 (VDD VSS net3 net5) Inverter wp=360n wn=180n
 I10 (VDD VSS net5 enable enableb BLB) enabledInverter
ends BL

// Bit Cell
subckt BitCell VDD VSS WL BL BLB Q QB
parameters wp24=90n wn13=173n wn56=144n lpn=50n
        M1 (Q QB VSS VSS) NMOS_VTL w=wn13 l=lpn
        M2 (Q QB VDD VDD) PMOS_VTL w=wp24 l=lpn
        M3 (QB Q VSS VSS) NMOS_VTL w=wn13 l=lpn
        M4 (QB Q VDD VDD) PMOS_VTL w=wp24 l=lpn
        M5 (Q WL BL VSS) NMOS_VTL w=wn56 l=lpn
        M6 (QB WL BLB VSS) NMOS_VTL w=wn56 l=lpn
ends BitCell

// Cell name: SenseAmp
// Function: High-speed sense-amplifier circuit
// Inputs: bit, bitbar, SE
// Outputs: out, outbar
subckt SenseAmp VDD VSS bit bitbar SE out outbar
parameters wp=180n wn=90n ln=50n lp=50n
 I0 (VDD VSS SE SEbar) Inverter
 M0 (outbar SE VDD VDD) PMOS_VTL w=wp l=lp
 M1 (outbar net0 VDD VDD) PMOS_VTL w=wp l=lp
 M2 (net0 net0 VDD VDD) PMOS_VTL w=wp l=lp
 M3 (net1 net1 VDD VDD) PMOS_VTL w=wp l=lp
 M4 (out net1 VDD VDD) PMOS_VTL w=wp l=lp
 M5 (out SE VDD VDD) PMOS_VTL w=wp l=lp
 M6 (outbar net2 VSS VSS) NMOS_VTL w=wn l=ln
 M7 (net0 net3 VSS VSS) NMOS_VTL w=wn l=ln
 M8 (net1 net2 VSS VSS) NMOS_VTL w=wn l=ln
 M9 (out net3 VSS VSS) NMOS_VTL w=wn l=ln
 M10 (net2 SEbar bit VDD) PMOS_VTL w=wp l=lp
 M11 (net3 SEbar bitbar VDD) PMOS_VTL w=wp l=lp
 M12 (net2 SEbar VSS VSS) NMOS_VTL w=wn l=ln      
 M13 (net3 SEbar VSS VSS) NMOS_VTL w=wn l=ln
ends SenseAmp

 I0 (VDD VSS IN INB) Inverter wp=720n wn=360n
 // Column decoder
 W0 ( VDD VSS IN IN IN IN IN INB INB INB INB INB word00000 word00001 word00010 word00011 word00100 word00101 word00110 word00111 word01000 word01001 word01010 word01011 word01100 word01101 word01110 word01111 word10000 word10001 word10010 word10011 word10100 word10101 word10110 word10111 word11000 word11001 word11010 word11011 word11100 word11101 word11110 word11111 ) wordDecoder

subckt rowdecoder VDD VSS INB read write wordline 
 // Row decoder
 N1 (INB INB INB INB pre0 VDD VSS) NAND4
 N2 (INB INB INB INB pre1 VDD VSS) NAND4
 N3 (pre0 pre1 prewordline VDD VSS) NOR2
 N4 (read write readorwrite VDD VSS) NOR2
 N5 (VDD VSS readorwrite rwb) Inverter
 N6 (prewordline rwb wordlineb VDD VSS) NAND2
 N7 (VDD VSS wordlineb wordline) Inverter
ends rowdecoder

 R0 (VDD VSS INB read write wordline) rowdecoder

 // Bit line handler
 B0 (word00000 write read data BL BLB VDD VSS) BL

 // Effective capacitances for bit lines
 Cap0 (BL VSS) capacitor c=64f
 Cap1 (BLB VSS) capacitor c=64f
 Cap2 (wordline VSS) capacitor c=49.28f

 // Sense amp enable
 I4 (VDD VSS read read0) Inverter
 I5 (VDD VSS read0 read1) Inverter
 I6 (VDD VSS read1 read2) Inverter
 I7 (VDD VSS read2 read3) Inverter
 A1 (read3 word00000 saeb VDD VSS) NAND2
 I3 (VDD VSS saeb sae) Inverter
 
 I8 (VDD VSS outbar outbuf) Inverter
 I9 (VDD VSS outbuf outbuf2) Inverter
 // Bit cell
 BC0 (VDD VSS wordline BL BLB Q QB) BitCell

 // Sense amp
 SA0 (VDD VSS BL BLB sae out outbar) SenseAmp
